IMMEDIATE_INSTRS=0, IFTHEN_INSTRS=0, EXTEND_INSTRS=00, INTERWORK_INSTRS=00
Instruction Set Attributes Register 1
EXTEND_INSTRS | Indicates the supported Extend instructions 0 (00): None supported, ARMv7-M reserved 1 (01): Adds support for the SXTB, SXTH, UXTB, and UXTH instructions 2 (10): As for 1, and adds support for the SXTAB, SXTAB16, SXTAH, SXTB16, UXTAB, UXTAB16, UXTAH, and UXTB16 instructions |
IFTHEN_INSTRS | Indicates the supported IfThen instructions 0 (0): None supported, ARMv7-M reserved 1 (1): Adds support for the IT instructions, and for the IT bits in the PSRs |
IMMEDIATE_INSTRS | Indicates the support for data-processing instructions with long immediate 0 (0): None supported, ARMv7-M reserved 1 (1): Adds support for the ADDW, MOVW, MOVT, and SUBW instructions |
INTERWORK_INSTRS | Indicates the supported Interworking instructions 0 (00): None supported, ARMv7-M reserved 1 (01): Adds support for the BX instruction, and the T bit in the PSR 2 (10): As for 1, and adds support for the BLX instruction, and PC loads have BX-like behavior 3 (11): ARMv7-M reserved |